1. Field of the Invention
The present invention generally relates to a process for fabricating a flip chip package. More particularly, the present invention relates to a bump process for fabricating a flip chip package.
2. Description of the Related Art
Flip chip bonding technology is a technique for connecting a chip to a carrier. Before the connection, a chip with an active surface having an array of die pads thereon is provided. Thereafter, bumps are formed respectively on the die pads of the chip. The chip is flipped over and bonded with the carrier such that the die pads of the chip are electrically and structurally connected to the contacts of the carrier via the bumps. Through circuits embedded within the carrier, the chip is able to communicate electrically with an external device. Since flip chip bonding technique is able to produce a flip chip package with a high pin count, a small package area and a short transmission path, flip chip bonding processes are widely adopted in the fabrication of high grade chip packages.
FIGS. 1A through 1H are schematic cross-sectional views showing the steps of forming a convention flip chip package. As shown in FIG. 1A, a chip 102 with an active surface 104 having a plurality of die pads 106 thereon is provided. A passivation layer 108 that exposes a portion of these die pads 106 is formed over the active surface 104 of the chip 102. In addition, a plurality of under bump metallurgy (UBM) layers 110 is formed over various die pads 106. Furthermore, a stress buffer layer (SBL) 112 that exposes various UBM layers 110 is formed over the passivation layer 108. The stress buffer layer (SBL) 112 is fabricated using a material such as benzocyclobutene (BCB).
As shown in FIG. 1B, a photoresist layer 114 is formed on the active surface 104 of the chip 102. Thereafter, as shown in FIG. 1C, a plurality of openings 116 is formed on the photoresist layer 114 by performing photo-exposure and chemical development process. The openings 116 expose various under bump metallurgy layers 110 so that the die pads 106 are indirectly exposed.
As shown in FIG. 1D, a printing process is carried out to fill conductive material into the openings 116. Thereafter, a reflow process is performed so that the conductive material inside the openings 116 is cured to form a plurality of short cylindrical bumps 118. Afterwards, the photoresist layer 114 is removed to expose the sides of the bumps 118 as shown in FIG. 1E. Another reflow process is carried out so that the cylindrical bumps 118 are transformed into spherical bumps 118 as shown in FIG. 1F. Since a chip can be obtained by cutting a wafer, the aforementioned steps can be applied to a wafer prior to cutting the wafer to produce individual chips 102 with bumps 118.
As shown in FIG. 1G, the chip 102 is flipped over and then the bumps 118 are connected to bump pads 12 on the surface of a substrate 10. Hence, the chip 102 is electrically and structurally connected to the substrate 10 via the bumps 118. Finally, as shown in FIG. 1H, underfill material is injected to the space between the chip 102 and the substrate 10. Thereafter, the underfill material is cured to form an underfill layer 20. The underfill layer 20 provides to buffer any thermal stress between the chip 102 and the substrate 10 so that cracks at the junction between the bumps 118 and the chip 102 or the substrate 10 is greatly minimized.
However, the conventional flip chip fabricating process has the following drawbacks: 1. Since a photoresist layer and a photolithographic process are required for fabricating cylindrical bumps, therefore the fabrication cost of the flip chip package is increased. 2. The printing process deployed to form bumps in the openings often produces voids close to the bottom section of the bumps and hence the reliability of the chip connection in the package is poor. 3. The conventional underfill dispensing process frequently produces voids in the underfill layer. Too many voids in the underfill layer may lead to a delamination between the chip and the substrate. Accordingly, the reliability of the package is reduced.